The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device (hereinafter called a "nonvolatile memory device"), and more particularly, to a method for manufacturing a nonvolatile semiconductor memory device which prevents operational degradation and maintains isolation between transistors.
In a data processing system, memory devices for storing information are extremely important. As such memory devices, there are volatile memory devices that lose memory contents when power is interrupted and nonvolatile memory devices that retain memory contents even without power supply. Nonvolatile memory devices can be roughly divided into read only memory (ROM) devices that can read data stored therein and electrically erasable & programmable read only memory (EEPROM) devices that can modify the stored data by employing an electrical method. A flash memory device, all the contents therein being able to be erased simultaneously, is an example of an EEPROM. As a nonvolatile memory device, the EEPROM widely uses structure adopting a MOS floating gate electrode which is composed of conductive material electrically isolated from the semiconductor substrate. Such a floating gate electrode is capacitively combined with the semiconductor substrate and senses a charge state. Accordingly, the MOS transistor is "on" or "off" depending on whether there is a charge on the floating gate electrode, and thereby stores a data bit "1" or "0." For injecting and removing a charge to the floating gate electrode, hot electrons generated by avalanche breakdown, and a tunneling effect can be used.
Meanwhile, the nonvolatile memory device needs a high voltage (approximately 20 V) for writing and erasing data. The voltage can be obtained from a booster circuit of a periphery circuit portion. Thus, isolation between transistors is an extremely important factor for maintaining the function of the device. The field oxide film thickness and the impurity concentration of an impurity region, used for separating the active regions, are key factors for determining transistor isolation characteristics. The field oxide film is formed thickly to improve isolation, specifically in EEPROM and flash memory devices, because the field oxide film becomes thinner as the manufacturing process progresses and a predetermined thickness is required after the last step to ensure isolation capability for a high voltage transistor. In addition, transistor isolation becomes a more important factor as the device becomes highly integrated. In contrast, however, the field oxide film thickness has to be made thinner as device integration increases.
FIG. 1 is a section view showing the conventional nonvolatile memory device before an intermediate isolating layer for a metal wire is deposited. In more detail, the nonvolatile memory device comprises a memory cell array (portion A) consisting of floating gate 301 for storing data and control gate 302 for receiving an applied voltage, and a peripheral circuit portion (portion B) consisting of various driving transistors.
The cell array includes an N-type impurity region (N-well 101) and a P-type impurity region (P-well 102) on P-type substrate 100. In addition, N-type high concentration impurity region 104 is formed near the surface of the substrate and serves as a source or drain. A lower dielectric layer (tunnel oxide film 201) consisting of a pure oxide film or an oxynitride film for utilizing a tunneling effect is formed on the substrate. A floating gate 301 is provided on lower dielectric layer 201, and control gate 302 is formed on floating gate 301 having upper dielectric layer 210 as a medium. Floating gate 301 (first electrode layer) is located between upper and lower dielectric layers 201 and 210 and is generally formed of N-type impurity doped polysilicon. Control gate 302 (second electrode layer) is located on upper dielectric layer 210 and is generally formed of polysilicon and a metal-silicon composite so as to obtain low resistance. In addition, upper dielectric layer 210 is formed by an oxide-nitride-oxide (ONO) film in order to obtain high capacitance.
Peripheral circuit portion B includes a P-type impurity region (P-well 102) and an N-type impurity region (N-well 101) formed on P-type semiconductor substrate 100. The peripheral circuit portion structure is formed by a general CMOS process technique. A high concentration N-type impurity region 104 in a P-type impurity region (p-well 102) for making a CMOS N-type transistor is formed simultaneously with the cell array (portion A). Thus, N-type impurity region 104 can serve as a source or drain. On the contrary, the CMOS P-type transistor is formed by a high concentration P-type impurity region 105 in the N-type impurity region (N-well 101). Thus, the P-type impurity region 105 can serve as a source or drain. In addition, the N-type transistor of the peripheral circuit portion is electrically isolated by employing field oxide film 200 and high concentration P-type impurity region 103 which is located below field oxide film 200. The P-type transistor is isolated by employing only field oxide film 200. In addition, the control gate electrode 302 of a peripheral circuit portion transistor is formed by the same film as that of the second electrode layer of the cell array having gate oxide film 202 as a medium.
FIG. 2 to FIG. 9 are section views showing a method for manufacturing the nonvolatile memory device shown in FIG. 1 according to the process sequence.
In the same manner as shown in FIG. 1, the nonvolatile memory device includes a cell array (portion A) where a floating gate for storing data and a control gate for receiving an applied voltage are formed and a peripheral circuit portion (portion B) where various transistors required for driving the device are formed. Specifically, the peripheral circuit portion (B) of FIG. 4 to FIG. 9 is a part of portion B shown in FIG. 2 and FIG. 3, which is truncated for the convenience of explanation.
FIG. 2 shows the steps of forming an N-type impurity region (N-well region 101) and a P-type impurity region (P-well region 102) on the peripheral circuit portion and cell array of a semiconductor substrate by a conventional CMOS process.
First, an N-type impurity is injected into the peripheral circuit portion of P-type silicon substrate 100 and into a predetermined region of the cell array by employing a general photo-etching process and ion-implantation technique. Then, the resultant structure is heat-treated and the N-type impurity is diffused to the desired depth, thereby forming N-type impurity region (N-well 101). Then, in the same manner as that of forming N-type impurity region 101, a P-type impurity is injected into the peripheral circuit portion of P-type silicon substrate 100 and into predetermined N-well region 101 of the cell array by employing a general photo-etching process and ion-implantation technique. Then, the resultant structure is heat-treated and the P-type impurity is diffused to the desired depth, thereby forming a P-type impurity region (P-well 102).
Then, to electrically isolate the devices, field oxide film 200 is formed to a thickness of 5,000 .ANG. to 6,000 .ANG. by employing a general photo-etching process and a device isolation process (for example, LOCOS). In order to further strengthen the electrical isolation prior to forming the field oxide film, a channel-stopping impurity (for example, a high concentration boron) is ion-implanted into the region where the field oxide film of P-type impurity region 102 and the cell array region is to be grown. Thus, the channel-stopping impurity can be diffused to the part of an active region when field oxide film 200 is formed. Then, the unnecessary film material (for example, an oxide or nitride film) which is formed when the field oxide film is formed on a substrate and an ion-implantation is performed, is removed. Thus, the surface of the substrate is confined by field oxide film 200.
FIG. 3 shows the steps of forming first dielectric layer 201 and first conductive layer 301 on the entire surface of the substrate where field oxide film 200 is formed.
In more detail, first dielectric layer 201 (as a lower dielectric layer) is formed by an oxide film or oxynitride film having a thickness of 70 .ANG. to 100 .ANG. all over the substrate where isolated field oxide film 200 is formed. The first dielectric layer is used as a tunnel oxide film. Then, as a conductive material for forming a floating gate, first conductive layer 301 is formed by depositing polycrystalline silicon to a thickness of 1,500 .ANG. to 2,000 .ANG. on lower dielectric layer 201, by employing a CVD method. Then, first conductive layer 301 is made conductive by depositing POCl.sub.3 which contains a large quantity of phosphorous.
FIG. 4 shows the steps of forming first conductive pattern 301a by etching the above-formed first conductive layer 301.
First, a photoresist is coated onto first dielectric layer 201 and the resultant structure is patterned, to thereby form photo-resist pattern 400 partially in the cell array. Then, first conductive layer 301 formed in the peripheral circuit portion and in part of the cell array is selectively etched using the photo-resist pattern as an etching mask, to 10 thereby form first conductive pattern 301a.
FIG. 5 shows the steps of forming second dielectric layer 210 on the entire surface of first conductive pattern 301a and substrate 100.
In more detail, after photoresist pattern 400 used for the etching process is removed, second dielectric layer 210 is formed all over first conductive pattern 301a and substrate 100. Second dielectric layer 210 is formed as a composite layer of oxide/nitride/oxide (ONO).
FIG. 6 shows the steps of patterning second dielectric layer 210 and forming second dielectric pattern 210a.
First, a photoresist is deposited on second dielectric layer 210 and the resultant structure is patterned, to thereby form photoresist pattern 400a in a cell array. Then, in order to manufacture a transistor in the peripheral circuit portion, second dielectric layer 210 and first dielectric layer 201 formed in the peripheral circuit portion are etched using photoresist pattern 400a as an etching mask. When second dielectric layer 210 formed in the peripheral circuit portion is completely etched, second dielectric pattern 210a is formed in the cell array.
Specifically, when second dielectric layer 210 consisting of an ONO film formed in the peripheral circuit portion is etched, the thickness of field oxide film 200 is reduced by as much as the dimension 500 since the selective ratio of ONO film-to-field oxide film 200 or ONO film-to-first dielectric layer 201 is generally low, i.e., 2:1 to 5:1. In addition, micro-pitting 600 is generated on the surface of the silicon where a transistor is to be formed. The decrease of the field oxide film and the micro-pitting generated on the surface of the silicon deteriorate transistor isolation and thus cause operational degradation.
FIG. 7 shows the steps of forming second conductive layer 302 on the entire surface of the substrate where second dielectric pattern 210a is formed.
First, photoresist pattern 400a employed for etching second dielectric layer 210 of the peripheral circuit portion is removed. After an oxide film as third dielectric layer 202 is formed to a thickness of 100 .ANG. to 300 .ANG., a polycrystalline silicon is formed to a thickness of 1,500 .ANG. on the entire surface of the peripheral circuit portion and cell array. At this time, the cell array is not oxidized due to second dielectric pattern 210a consisting of an ONO film. Then, a refractory metal silicide layer (not shown) is formed to a thickness of 1,500 .ANG. on the polycrystalline silicon, to thereby complete second conductive layer 302.
FIG. 8 shows the steps of patterning second conductive layer 302.
A photoresist is deposited on second conductive layer 302 and the resultant structure is patterned, to thereby form photoresist pattern 400b in the cell array and in part of the peripheral circuit portion. Then, second conductive layer 302, a metal silicide layer (not shown), second dielectric pattern 210a and first conductive pattern 301a are selectively etched, using photoresist pattern 400b as an etching mask.
FIG. 9 shows the steps of forming gate electrode 302a in the peripheral circuit portion, control gate 302b in a cell array, floating gate 301b and an upper dielectric layer 210b.
First, photoresist pattern 400b is removed and an N-type impurity is ion-implanted by a self-alignment method. Then, the resultant structure is heat-treated, to thereby form N-type impurity region 104 in the cell array. Thus, control gate 302b consisting of second conductive layer 302 and a metal silicide (not shown) is formed and upper dielectric layer 210b and floating gate 301b are formed in the lower portion of control gate 302b.
In the nonvolatile semiconductor memory device manufactured according to the above-described method, a process for removing the first conductive layer, the second dielectric layer and the first dielectric layer in the peripheral circuit portion is inevitable since a transistor of the peripheral circuit portion which requires a high operation voltage, for example, approximately 20V, has to be formed. Specifically, when the first and second dielectric layers of the peripheral circuit portion are removed, the selective ratio of the second dielectric layer to a field oxide film or the second dielectric layer to the first dielectric layer is not high. Therefore, the field oxide film becomes much thinner. In addition, micro-pitting is generated in the surface of the silicon where a transistor is to be formed. The decrease of the field oxide film and the micro pitting generated on the surface of the silicon weaken transistor isolation and cause operation degradation.